In the prior arts a twin MONOS memory erase is achieved by applying a positive bias to the bit diffusion and a negative bias to the control gate. The other word gate and substrate terminals are grounded. But the voltage of word gate channel adjacent to the control gate can dramatically influence erase...http://www.google.fr/patents/US20020067641?utm_source=gb-gplus-shareBrevet US20020067641 - Usage of word voltage assistance in twin MONOS cell during program and erase
Usage of word voltage assistance in twin MONOS cell during program and erase
Numéro de demande: 10/005,932 Numéro de publication: US 2002/0067641 A1 Date de dépôt: 5 déc. 2001 Brevet délivré: US6477088 ( Date de délivrance 5 nov. 2002)
