A technique for providing adaptive 128-bit load and store operations to support architecture extensions for computations on a 128-bit quadruple precision format, in which a single set of load and store instructions provides for save and restore operations on both 80-bit and 128-bit floating...http://www.google.fr/patents/US5764959?utm_source=gb-gplus-shareBrevet US5764959 - Adaptive 128-bit floating point load and store instructions for quad-precision compatibility
Adaptive 128-bit floating point load and store instructions for quad ...
