The present invention provides a method using a damascene-gate process to improve the transport properties of FETs through strain Si. Changes in mobility and FET characteristics are deliberately made in a Si or silicon-on-insulator (SOI) structure through the introduction of local strain in the channel...http://www.google.fr/patents/US20050045972?utm_source=gb-gplus-shareBrevet US20050045972 - Strained silicon-channel mosfet using a damascene gate process
Strained silicon-channel mosfet using a damascene gate process
Numéro de demande: 10/650,400 Numéro de publication: US 2005/0045972 A1 Date de dépôt: 28 août 2003 Brevet délivré: US6916694 ( Date de délivrance 12 juil. 2005)
