An integrated circuit, when designed, must adhere to timing constraints while attempting to minimize circuit area. In order to adhere to timing specifications while arriving at a near-optimal circuit surface area, an iterative process is used which selectively increases logic gates sizes by accessing...http://www.google.fr/patents/US5619418?utm_source=gb-gplus-shareBrevet US5619418 - Logic gate size optimization process for an integrated circuit whereby circuit speed is improved while circuit area is optimized
Logic gate size optimization process for an integrated circuit whereby ...
