An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator, wherein the cache controller is operative...http://www.google.fr/patents/US7594069?utm_source=gb-gplus-shareBrevet US7594069 - Method and apparatus for single instruction multiple data caching
Method and apparatus for single instruction multiple data caching
