A method and apparatus for a mechanism for handling explicit writeback in a cache coherent multi-node architecture is described. In one embodiment, the invention is a method. The method includes receiving a read request relating to a first line of data in a coherent memory system. The method further...http://www.google.fr/patents/US20020178210?utm_source=gb-gplus-shareBrevet US20020178210 - Mechanism for handling explicit writeback in a cache coherent multi-node architecture
Mechanism for handling explicit writeback in a cache coherent multi-node ...
Numéro de demande: 09/823,791 Numéro de publication: US 2002/0178210 A1 Date de dépôt: 31 mars 2001 Brevet délivré: US6842830 ( Date de délivrance 11 janv. 2005)
