Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster, to create a buffer tree spanning...http://www.google.fr/patents/US7484199?utm_source=gb-gplus-shareBrevet US7484199 - Buffer insertion to reduce wirelength in VLSI circuits
Buffer insertion to reduce wirelength in VLSI circuits
