A sign-off method for use in verifying of embedded test structures in a circuit design extracts a description of all embedded test structures from a circuit description to create a test connection map file, and verifies the connections of the test structures to circuit pins or nets, creates verification...http://www.google.fr/patents/US6725435?utm_source=gb-gplus-shareBrevet US6725435 - Method and program product for completing a circuit design having embedded test structures
Method and program product for completing a circuit design having embedded ...
