A method for testing a programmable logic device having defined programmable function blocks with programmable interconnects follows steps of (a) configuring, by programming, two or more similar groups of the function blocks and interconnects into identical state machines; (b) operating the programmed...http://www.google.fr/patents/US20020078412?utm_source=gb-gplus-shareBrevet US20020078412 - Built-in self test for a programmable logic device using linear feedback shift registers and hierarchical signature generation
Built-in self test for a programmable logic device using linear feedback ...
