Described is a high-speed/low-speed interface for data processing systems which interface may be implemented on a single LSI MOS chip having a first portion fabricated to include high-speed circuitry to be clocked by a high-speed clock, a second portion fabricated to include low-speed circuitry to be...http://www.google.fr/patents/US3980993?utm_source=gb-gplus-shareBrevet US3980993 - High-speed/low-speed interface for data processing systems
High-speed/low-speed interface for data processing systems
