Automatic generation of post-layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints. A new circuit element is assigned...http://www.google.fr/patents/US5825661?utm_source=gb-gplus-shareBrevet US5825661 - Method and apparatus for automatic post-layout optimization of an integrated circuit
Method and apparatus for automatic post-layout optimization of an integrated ...
