A microprocessor and a data processor therefor which have separate data and instruction buses, and wherein a data address and an instruction address are output over a single address bus in a time-shared manner, thereby allowing a data access and an instruction access to be pipelined without the need...http://www.google.fr/patents/US6205536?utm_source=gb-gplus-shareBrevet US6205536 - Combined Instruction and address caching system using independent buses
Combined Instruction and address caching system using independent buses
