An integrated processor is provided that employs an improved address decoding method during bus cycles of an external master. An external PCI master may initiate a cycle (either memory or I/O) on the PCI bus by asserting an address signal on the PCI bus along with the FRAME signal which indicates...http://www.google.fr/patents/US5842041?utm_source=gb-gplus-shareBrevet US5842041 - Computer system employing a control signal indicative of whether address is within address space of devices on processor local bus
Computer system employing a control signal indicative of whether address is ...
