A semiconductor memory device with a built-in cache memory comprises a memory cell array (1). The memory cell array (1) is divided into a plurality of blocks (B1 to B16). Each block is divided into a plurality of sub blocks each having a plurality of columns. At the time of a cache hit, block address...http://www.google.fr/patents/US5226139?utm_source=gb-gplus-shareBrevet US5226139 - Semiconductor memory device with a built-in cache memory and operating method thereof
Semiconductor memory device with a built-in cache memory and operating ...
