A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path, and at least one capacitor connecting the load path transversely to the signal path. A phase detector receives...http://www.google.fr/patents/US5471512?utm_source=gb-gplus-shareBrevet US5471512 - Phase-locked loop configuration
