A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and correction. A primary feature is the recognition...http://www.google.fr/patents/US5754753?utm_source=gb-gplus-shareBrevet US5754753 - Multiple-bit error correction in computer main memory
Multiple-bit error correction in computer main memory
