A high speed low power data transfer bus circuit that reduces bus power consumption by imposing a limited, controlled voltage swing on the associated data bus. In one embodiment, an inverter is coupled with a pMOS pass transistor and an nMOS discharge transistor, and the combination is coupled with a...http://www.google.fr/patents/US6417697?utm_source=gb-gplus-shareBrevet US6417697 - Circuit technique for high speed low power data transfer bus
Circuit technique for high speed low power data transfer bus
