A circuit for synchronizing the phase output of a clock relative to multiple asynchronous input trigger signals. A clock signal is directed as an input to a delay line having spaced output taps to produce a plurality of phase displaced clock signals, which are directed as inputs to a latch circuit. An...http://www.google.fr/patents/US5015871?utm_source=gb-gplus-shareBrevet US5015871 - Multiple external asynchronous triggers circuit
