A static logic signal to dynamic logic interface that produces a monotonic output. An inverse of a dynamic logic evaluate clock is fed to the clock input of a transparent latch with clock and enable inputs. A delayed version of the inverse of the evaluate clock is generated by a delay element. The delayed...http://www.google.fr/patents/US6377096?utm_source=gb-gplus-shareBrevet US6377096 - Static to dynamic logic interface circuit
