Based on a phase locked loop (PC1, CP1, VCXO) which receives an incoming data signal (DS) and generates a recovered clock signal (RC), in the event that this incoming data signal (DS) includes low frequency cycling, false phase locking can occur, consequently leading to impaired operation; in order...http://www.google.fr/patents/US5670913?utm_source=gb-gplus-shareBrevet US5670913 - Phase locked loop circuit with false locking detector and a lock acquisition sweep
Phase locked loop circuit with false locking detector and a lock acquisition ...
