A method for testing an integrated circuit memory device includes applying a sequence of test pulses to a memory cell on the device, where the test pulses result in current through the memory cell having an amplitude dependent on the test pulse. Resistance in the memory cell is measured in response to...http://www.google.fr/patents/US20090175071?utm_source=gb-gplus-shareBrevet US20090175071 - PHASE CHANGE MEMORY DYNAMIC RESISTANCE TEST AND MANUFACTURING METHODS
PHASE CHANGE MEMORY DYNAMIC RESISTANCE TEST AND MANUFACTURING METHODS
Numéro de demande: 11/970,348 Numéro de publication: US 2009/0175071 A1 Date de dépôt: 7 janv. 2008 Brevet délivré: US7639527 ( Date de délivrance 29 déc. 2009)
