In a memory cell, the substrate contact region of an NMOS transistor and the well contact region of a PMOS transistor are arranged perpendicularly to a floating gate. In a cell array, the memory cell and another memory cell arranged axisymmetrically with respect to the memory cell are alternately arranged...http://www.google.fr/patents/US6995436?utm_source=gb-gplus-shareBrevet US6995436 - Nonvolatile semiconductor memory device
