A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity....http://www.google.fr/patents/US5479641?utm_source=gb-gplus-shareBrevet US5479641 - Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking
Method and apparatus for overlapped timing of cache operations including ...
