A logic emulation system for emulating the operation of a circuit. A uniform routing architecture is provided where a first set of selectors (multiplexers) is coupled to a set of shift registers that are in turn coupled to a second set of selectors. The outputs of the second set of selectors are coupled...http://www.google.fr/patents/US5923865?utm_source=gb-gplus-shareBrevet US5923865 - Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
Emulation system having multiple emulated clock cycles per emulator clock ...
