An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the...http://www.google.fr/patents/US7646218?utm_source=gb-gplus-shareBrevet US7646218 - Architecture and interconnect scheme for programmable logic circuits
Architecture and interconnect scheme for programmable logic circuits
