Memory cell transistors are provided in which pillar structures or column structures (12, 12a, 14, and 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the pillar structures or column structures (12, 12a, 14, and 14a). The...http://www.google.fr/patents/US5379255?utm_source=gb-gplus-shareBrevet US5379255 - Three dimensional famos memory devices and methods of fabricating
Three dimensional famos memory devices and methods of fabricating
