An instruction execution unit having an instruction format with four addresses. Two of the addresses may be defined as sources for operands. Two of the four addresses may be defined as a destination for the result of the computational unit and a pointer updated by a pointer pipeline. There are two arithmetic...http://www.google.fr/patents/US5560039?utm_source=gb-gplus-shareBrevet US5560039 - Apparatus and method for a four address arithmetic unit
Apparatus and method for a four address arithmetic unit
