A dynamically configurable portion of a cache shared between central processing and graphics units in a highly integrated multimedia processor is engaged as a secondary level in a hierarchical texture cache architecture. The graphics unit includes a small multi-ported L1 texture cache local to its 2D/3D...http://www.google.fr/patents/US6483516?utm_source=gb-gplus-shareBrevet US6483516 - Hierarchical texture cache
