Antifuses are provided which include first and second conductive layers and an antifuse layer positioned between the first and second conductive layers. The antifuse layer includes at least one oxide layer positioned between two amorphous silicon layers. Interconnect structures and programmable logic...http://www.google.fr/patents/US5970372?utm_source=gb-gplus-shareBrevet US5970372 - Method of forming multilayer amorphous silicon antifuse
Method of forming multilayer amorphous silicon antifuse
