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82a, LOOKUP MICROINSTRUCTIONS
82b, FORM REGISTER FILE ADDRESSES
31 3029 2827 26 25 24 23 2221 20 19 18 17 1615 14 13 12 1] 10 9 8 7 6 5 4 3 2 1 0
BR BIT H—+"H—+—1—+"H—+—^—l—+—I-——+—•—+—I—+——I—+—• 1"H I—+--H—H 1—+—
B" I 1 I l I 1 I shftjA/B Rel Src(aluB) | amount |Bv| Branch Address | defbr |GT| branch bit
(setCC) +—+--+--+—I—+—+_-+~H—+—\—+—H h~+-H—H—+—+—H—+—+--+--+—I-—h—+--+—+—I—+—
Defbr => gives number of defered instructions (must be less/equal max_allowed (or BR_ev field))
Defered instructions can NOT be branch instructions
Br_Byte => (EQ assumes GT, NEQ assumes NT)
Can have defer = 3 on conditional branchs following br-bit or br-byte
BRANCH INSTRUCTION FOR PROCESSOR
WITH BRANCHING DEPENDENT ON A
SPECIFIED BIT IN A REGISTER
This invention relates to branch instructions.
Parallel processing is an efficient form of information processing of concurrent events in a computing process. Parallel processing demands concurrent execution of many programs 10 in a computer. Sequential processing or serial processing has all tasks performed sequentially at a single station whereas, pipelined processing has tasks performed at specialized stations. Computer code whether executed in parallel processing, pipelined or sequential processing machines involves 15 branches in which an instruction stream may execute in a sequence and branch from the sequence to a different sequence of instructions.
BRIEF DESCRIPTION OF THE DRAWINGS 20
FIG. 1 is a block diagram of a communication system employing a processor.
FIG. 2 is a detailed block diagram of the processor.
FIG. 3 is a block diagram of a microengine used in the 25 processor of FIGS. 1 and 2.
FIG. 4 is a diagram of a pipeline in the microengine.
FIG. 5 shows exemplary formats for branch instructions.
FIG. 6 is a block diagram of general purpose registers.
Referring to FIG. 1, a communication system 10 includes a processor 12. In one embodiment, the processor is a hardware-based multithreaded processor 12. The processor 12 is 35 coupled to a bus such as a PCI bus 14, a memory system 16 and a second bus 18. The system 10 is especially useful for tasks that can be broken into parallel sub-tasks or functions. Specifically hardware-based multithreaded processor 12 is useful for tasks that are bandwidth oriented rather than 40 latency oriented. The hardware-based multithreaded processor 12 has multiple microengines 22 each with multiple hardware controlled threads that can be simultaneously active and independently work on a task.
The hardware-based multithreaded processor 12 also 45 includes a central controller 20 that assists in loading microcode control for other resources of the hardware-based multithreaded processor 12 and performs other general purpose computer type functions such as handling protocols, exceptions, extra support for packet processing where the 50 microengines pass the packets off for more detailed processing such as in boundary conditions. In one embodiment, the processor 20 is a Strong Arm® (Arm is a trademark of ARM Limited, United Kingdom) based architecture. The general purpose microprocessor 20 has an operating system. Through 55 the operating system the processor 20 can call functions to operate on microengines 22a-22f. The processor 20 can use any supported operating system preferably a real time operating system. For the core processor implemented as a Strong Arm architecture, operating systems such as, MicrosoftNT® 60 real time, VXWorks and uCUS, a freeware operating system available over the Internet, can be used.
The hardware-based multithreaded processor 12 also includes a plurality of function microengines 22a-22f. Functional microengines (microengines) 22a-22/each maintain a 65 plurality of program counters in hardware and states associated with the program counters. Effectively, a corresponding
plurality of sets of threads can be simultaneously active on each of the microengines 22a-22f while only one is actually operating at any one time.
Microengines 22a-22/each have capabilities for processing four hardware threads. The microengines 22a-22/operate with shared resources including memory system 16 and bus interfaces 24 and 28. The memory system 16 includes a Synchronous Dynamic Random Access Memory (SDRAM) controller 26a and a Static Random Access Memory (SRAM) controller 26b. SDRAM memory 16a and SDRAM controller 26a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets. The SRAM controller 26b and SRAM memory 16b are used in, e.g., networking packet processing, postscript processor, or as a processor for a storage subsystem, i.e., RAID disk storage, or for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and so forth.
The processor 12 includes a bus interface 28 that couples the processor to the second bus 18. Bus interface 28 in one embodiment couples the processor 12 to the so-called FBUS 18 (FIFO bus). The processor 12 includes a second interface e.g., a PCI bus interface 24 that couples other system components that reside on the PCI 14 bus to the processor 12. The PCI bus interface 24, provides a high speed data path 24a to the SDRAM memory 16a. Through that path data can be moved quickly from the SDRAM 16a through the PCI bus 14, via direct memory access (DMA) transfers.
Each of the functional units are coupled to one or more internal buses. The internal buses are dual, 32 bit buses (i.e., one bus for read and one for write). The hardware-based multithreaded processor 12 also is constructed such that the sum of the bandwidths of the internal buses in the processor 12 exceed the bandwidth of external buses coupled to the processor 12. The processor 12 includes an internal core processor bus 32, e.g., an ASB bus (Advanced System Bus) that couples the processor core 20 to the memory controller 26a, 26c and to an ASB translator 30 described below. The ASB bus is a subset of the so called AMBA bus that is used with the Strong Arm processor core. The processor 12 also includes a private bus 34 that couples the microengine units to SRAM controller 26b, ASB translator 30 and FBUS interface 28. A memory bus 38 couples the memory controller 26a, 26b to the bus interfaces 24 and 28 and memory system 16 including flashrom 16c used for boot operations and so forth.
Referring to FIG. 2, each of the microengines 22a-22/ includes an arbiter that examines flags to determine the available threads to be operated upon. Any thread from any of the microengines 22a-22/ can access the SDRAM controller 26a, SDRAM controller 26b or FBUS interface 28. The memory controllers 26a and 26b each include a plurality of queues to store outstanding memory reference requests. The FBUS interface 28 supports Transmit and Receive flags for each port that a MAC device supports, along with an Interrupt flag indicating when service is warranted. The FBUS interface 28 also includes a controller 28a that performs header processing of incoming packets from the FBUS 18. The controller 28a extracts the packet headers and performs a microprogrammable source/destination/protocol hashed lookup (used for address smoothing) in SRAM.
The core processor 20 accesses the shared resources. The core processor 20 has a direct communication to the SDRAM controller 26a to the bus interface 24 and to SRAM controller 26b via bus 32. However, to access the microengines 22a-22/ and transfer registers located at any of the microengines 22a-22/J the core processor 20 access the microengines 22a-22/via the ASB Translator 30 over bus 34. The ASB
translator 30 can physically reside in the FBUS interface 28, but logically is distinct. The ASB Translator 30 performs an address translation between FBUS microengine transfer register locations and core processor addresses (i.e., ASB bus) so that the core processor 20 can access registers belonging to 5 the microengines 22a-22c.
Although microengines 22 can use the register set to exchange data as described below, a scratchpad memory 27 is also provided to permit microengines to write data out to the memory for other microengines to read. The scratchpad 27 is 10 coupled to bus 34.
The processor core 20 includes a RISC core 50 implemented in a five stage pipeline performing a single cycle shift of one operand or two operands in a single cycle, provides multiplication support and 32 bit barrel shift support. This 15 RISC core 50 is a standard Strong Arm® architecture but it is implemented with a five stage pipeline for performance reasons. The processor core 20 also includes a 16 kilobyte instruction cache 52, an 8 kilobyte data cache 54 and a prefetch stream buffer 56. The core processor 20 performs 20 arithmetic operations in parallel with memory writes and instruction fetches. The core processor 20 interfaces with other functional units via the ARM defined ASB bus. The ASB bus is a 32-bit bi-directional bus 32.
Referring to FIG. 3, an exemplary microengine 22/ 2s includes a control store 70 that includes a RAM which stores a microprogram. The microprogram is loadable by the core processor 20. The microengine 22/also includes controller logic 72. The controller logic includes an instruction decoder 73 and program counter (PC) units 12a-12d. The four micro program counters 72a-72d are maintained in hardware. The microengine 22/also includes context event switching logic 74. Context event logic 74 receives messages (e.g., SEQ_#_EVENT_RESPONSE; FBI_EVENT_RESPONSE; SRAM_EVENT_RESPONSE; SDRAM_EVENT_RESPONSE; and ASB_EVENT_RESPONSE) from each one of 35 the shared resources, e.g., SRAM 26a, SDRAM 266, or processor core 20, control and status registers, and so forth. These messages provide information on whether a requested function has completed. Based on whether or not a function requested by a thread has completed and signaled completion, 40 the thread needs to wait for that completion signal, and if the thread is enabled to operate, then the thread is placed on an available thread list (not shown). The microengine 22/can have a maximum of e.g., 4 threads available.
In addition to event signals that are local to an executing 45 thread, the microengines 22 employ signaling states that are global. With signaling states, an executing thread can broadcast a signal state to all microengines 22. Receive Request or Available signal, any and all threads in the microengines can branch on these signaling states. These signaling states can be 50 used to determine availability of a resource or whether a resource is due for servicing.
The context event logic 74 has arbitration for the four (4) threads. In one embodiment, the arbitration is a round robin mechanism. Other techniques could be used including prior- 55 ity queuing or weighted fair queuing. The microengine 22/ also includes an execution box (EBOX) data path 76 that includes an arithmetic logic unit 76a and general purpose register set 76b. The arithmetic logic unit 76a performs arithmetic and logical functions as well as shift functions. The 60 arithmetic logic unit includes condition code bits that are used by instructions described below. The registers set 76b has a relatively large number of general purpose registers that are windowed as will be described so that they are relatively and absolutely addressable. The microengine 22/also includes a 65 write transfer register stack 78 and a read transfer stack 80. These registers are also windowed so that they are relatively
and absolutely addressable. Write transfer register stack 78 is where write data to a resource is located. Similarly, read register stack 80 is for return data from a shared resource. Subsequent to or concurrent with data arrival, an event signal from the respective shared resource e.g., the SRAM controller 26a, SDRAM controller 26b or core processor 20 will be provided to context event arbiter 74 which will then alert the thread that the data is available or has been sent. Both transfer register banks 78 and 80 are connected to the execution box (EBOX) 76 through a data path.
Referring to FIG. 4, the microengine datapath maintains a 5-stage micro-pipeline 82. This pipeline includes lookup of microinstruction words 82a, formation of the register file addresses 82b, read of operands from register file 82c, ALU, shift or compare operations 82^, and write-back of results to registers 82e. By providing a write-back data bypass into the ALU/shifter units, and by assuming the registers are implemented as a register file (ratherthan a RAM), the microengine can perform a simultaneous register file read and write, which completely hides the write operation.
The instruction set supported in the microengines 22a-22/ support conditional branches. The worst case conditional branch latency (not including jumps) occurs when the branch decision is a result of condition codes being set by the previous microcontrol instruction. The latency is shown below in Table 1:
where nx is pre-branch microword (nl sets cc's), cb is conditional branch, bx is post-branch microword and XX is an aborted microword
As shown in Table 1, it is not until cycle 4 that the condition codes of nl are set, and the branch decision can be made (which in this case causes the branch path to be looked up in cycle 5). The microengine 22/incurs a 2-cycle branch latency penalty because it must abort operations n2 and n3 (the 2 microwords directly after the branch) in the pipe, before the branch path begins to fill the pipe with operation bl. If the branch is not taken, no microwords are aborted and execution continues normally. The microengines have several mechanisms to reduce or eliminate the effective branch latency.
The microengines support selectable deferred branches. Selectable deferring branches are when a microengine allows 1 or 2 micro instructions after the branch to execute before the branch takes effect (i.e. the effect of the branch is "deferred" in time). Thus, if useful work can be found to fill the wasted cycles after the branch microword, then the branch latency can be hidden. A 1 -cycle deferred branch is shown below in Table 2 where n2 is allowed to execute after cb, but before b 1: