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ZIRCONIUM-DOPED TANTALUM OXIDE
FILMS
This application is a divisional of U.S. application Ser. No. 10/909,959 filed Aug. 2, 2004, now U.S. Pat. No. 7,601,649 which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
This application relates generally to semiconductor devices and device fabrication and, more particularly, to dielectric layers and their method of fabrication.
BACKGROUND
The semiconductor device industry has a market driven need to improve speed performance, improve its low static (off-state) power requirements, and lower production costs for its silicon based microelectronic products. In particular, there is continuous pressure to reduce the size of devices such as transistors. To reduce transistor size, the thickness of the silicon dioxide, Si02, gate dielectric is reduced in proportion to the shrinkage of the gate length. For example, a metaloxide-semiconductor field effect transistor (MOSFET) would use a 1.5 nm thick Si02 gate dielectric for a gate length of 70 nm. The ultimate goal is to fabricate increasingly smaller and more reliable integrated circuits (ICs) for use in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
Currently, the semiconductor industry relies on the ability to reduce or scale the dimensions of its basic devices, primarily, the silicon based MOSFET. This device scaling includes scaling the gate dielectric, which has primarily been fabricated using silicon dioxide. A thermally grown amorphous Si02 layer provides an electrically and thermodynamically stable material, where the interface of the Si02 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have created the need to use other dielectric materials as gate dielectrics.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 depicts an atomic layer deposition system for fabricating a dielectric layer containing a zirconium-doped tantalum oxide, according to various embodiments of the present invention.
FIG. 2 illustrates a flow diagram of elements for an embodiment of a method to form a dielectric layer containing a zirconium-doped tantalum oxide, according to various embodiments of the present invention.
FIG. 3 illustrates a flow diagram of elements for an embodiment of a method to form a dielectric layer containing a zirconium-doped tantalum oxide, according to the present invention.
FIG. 4 illustrates a flow diagram of elements for an embodiment of a method to form a dielectric layer containing a zirconium-doped tantalum oxide, according to the present invention.
FIG. 5 illustrates a flow diagram of elements for an embodiment of a method to form a dielectric layer containing a zirconium-doped tantalum oxide including substituting a zirconium sequence for a tantalum sequence, according to the present invention.
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FIG. 6 illustrates a flow diagram of elements for an embodiment of a method to form a dielectric layer containing a zirconium-doped tantalum oxide including commonly pulsing a zirconium precursor and a tantalum precursor, accord5 ing to the present invention.
FIG. 7 shows an embodiment of a configuration of a transistor having a dielectric layer containing an atomic layer deposited zirconium-doped tantalum oxide, according to the present invention. 10 FIG. 8 shows an embodiment of a configuration of a transistor with a floating gate having a dielectric layer containing an atomic layer deposited zirconium-doped tantalum oxide, according to the present invention.
FIG. 9 shows an embodiment of a configuration of a 15 capacitor having a dielectric layer containing an atomic layer deposited zirconium-doped tantalum oxide, according to the present invention.
FIG. 10 depicts an embodiment of a dielectric layer including a nanolaminate having at least one layer containing an 20 atomic layer deposited zirconium-doped tantalum oxide, according to the present invention.
FIG. 11 is a simplified diagram for an embodiment of a controller coupled to an electronic device, according to the present invention. 25 FIG. 12 illustrates a diagram for an embodiment of an electronic system having devices with a dielectric film containing an atomic layer deposited zirconium-doped tantalum oxide, according to the present invention.
30 DETAILED DESCRIPTION
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may
35 be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various
40 embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.
The terms wafer and substrate used in the following
45 description include any structure having an exposed surface with which to form an integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other
50 layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is under
55 stood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors or as semiconductors.
The term "horizontal" as used in this application is defined
60 as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as "on", "side" (as in "sidewall"), "higher", "lower", "over"
65 and "under" are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or sub
