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United States Patent  [li] Patent Number: 4,956,766
Dhopeshwarkar et al.  Date of Patent: Sep. 11,1990
 SYSTEMS FOR INHIBITING ERRORS CAUSED BY MEMORY CARTRIDGE INSERTION/REMOVAL USING AN IDLE LOOP
 Inventors: Dhirendra Dhopeshwarkar; Scott A.
Hightower; Mac A. Mathis; John W.
MehL all of Lexington, Ky.
 Assignee: International Business Machines
Corp., Armonk, N.Y.
 Appl. No.: 759,002
 Filed: JuL 25,1985
 Int. a.' .: G06F 9/04; G06F 11/20;
 U.S.CL 364/200; 364/239.9;
364/240.2; 364/240.7; 364/244.7; 364/249.8;
364/265.3; 364/267.8  Field of Search ... 364/200MS File, 900 MS File, 364/406, 567; 371/15, 16, 14; 273/148 B
 References Cited
U.S. PATENT DOCUMENTS
3.548.176 12/1970 Shutter 371/4
3.548.177 12/1970 Hartlipp et al 371/4
3.548.178 12/1970 Carnevale et al 371/4
3,971,925 7/1976 Wenninger et al 364/706
4,145,752 3/1979 Olander, Jr. et al 364/200
4,220,991 9/1980 Hamano et al 364/900
4,297,029 10/1981 Carlson 371/15
4,385,366 8/1983 Housey, Jr 364/900
4,400,783 8/1983 Locke 364/900
4,419,738 12/1983 Takahashi et al 364/900
4,454,591 6/1984 Lou 364/900
4,462,084 7/1984 Greenwood 364/900
4,481,587 11/1984 Daniels, Jr 364/567
4,523,296 6/1985 Healy 364/900
4,593,376 6/1986 Volk 364/900
4,596,390 6/1986 Studley 273/148 B
4,597,058 6/1986 Izumi et al 364/900
4,641,241 2/1987 Boram 364/409
IBM Tech. Dis. "Extension Device for a Personal Computer" vol. 27, No. 12, May 1985, pp. 6887-6889. Igel, "Variable-Performance Processors", IBM Technical Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3708-3710.
Globig, "Avoid Data Loss in Nonvolatile Memory", E.D.N. Electrical Design News, vol. 29, No. 18, Sep. 6, 1984, p. 225.
Nippon Denki K.K., "Data Memory Protecting Circuit", Patent Abstracts of Japan, vol. 6, No. 237 (p-157) , Nov. 25, 1982.
Matsushita Denki Sangyo K.K., "Privacy Protecting Device for Information in Memory", Patent Abstracts of Japan, vol. 8, No. 55 (P-260) , Mar. 13, 1984.
Primary Examiner—Archie E. Williams, Jr.
Assistant Examiner—Ayni Mohamed
Attorney, Agent, or Firm—Pollock, Vande Sande and
A computer system with provision for inserting/removing memory cartridges is improved by inhibiting erroneous operation as a result of noise produced on insertion/removal of a memory cartridge. Removable cartridges are connected/disconnected from a cartridge bus which is distinct from the system bus to which all other components are coupled. A controlled isolation is provided between the two buses. An idler routine ensures that in the absence of operator requested tasks the isolation prevents noise on the cartridge bus from reaching the system bus. When the processor executes an instruction (or only selected instructions) the isolation is disabled so that data/instructions can flow to/from the system and cartridge bus.
11 Claims, 1 Drawing Sheet
SYSTEMS FOR INHIBITING ERRORS CAUSED
BY MEMORY CARTRIDGE INSERTION/REMOVAL USING AN IDLE LOOP
FIELD OF THE INVENTION
The present invention relates to operator controlled computer systems, especially those systems which include provision for insertion/removal of one or more memory cartridges including read only storage and/or 10 random access memory.
Computer systems are used for a wide variety of tasks and are usually directed by an operator. It is now com- 13 mon in the computer industry to provide systems which include provision for the insertion/removal of memory cartridges, wherein the cartridges are either read only storage or read/write storage, or both. Examples of such systems include Wenninger et al U.S. Pat. No. 20 3,971,925; Hamano et al U.S. Pat. No. 4,220,991; Housey, Jr. U.S. Pat. No. 4,385,366; Takahashi et al U.S. Pat. No. 4,419,738; Lou U.S. Pat. No. 4,454,591 and Daniels, Jr. U.S. Pat. No. 4,481,587.
Wenninger et al for example provides an Adaptable 25 Programmed Calculator with a provision for plug in memory modules. These plug in ROMs can contain programs which can be executed by the user from the keyboard. Hamano deals with electronic cash registers which accept plug in random access (read/write) car- 30 tridges. Housey, Jr. describes a programmable device in which memory modules are selectively connected (such as by a plug in cartridge) read only memories to personalize the device. Takahashi describes a system in which a plug in read/write memory is used to transfer data to 35 a dedicated read/write memory in an electronic cash register. Lou describes an interface system for bus line control in an electronic calculator which employs, in addition to fixed memory modules, plug in memory modules. 40
Finally, Daniels, Jr. describes an apparatus for providing interchangeable keyboard functions, which apparatus includes insertable memory modules.
In some systems in which read only or read/write memory can be inserted/removed, operating instruc- 45 tions require that the insertion/removal be accomplished when the system is powered down, an example of such a system is the last-mentioned Daniels, Jr. patent He describes (see col. 8, lines 53 et seq) that after ROM insertion is effected, the "user then turns the scale SO 112 on by supplying power thereto". Video games and the PCjr are other examples of systems which include memory cartridges which can be inserted or removed, but in which the insertion/removal is effected when the system is powered down. In many cases, however, 55 while the insertion/removal of the memory cartridge effects a reset operation, data is to be retained across this reset; that is, data stored prior to the reset is to be retained so that it can be used after the reset. In other systems, or other applications of the same systems, there £0 is a desire to maintain the system powered up even though a memory cartridge may be inserted/removed. We have found that the insertion/removal of a cartridge can, in response to the electrical disturbances caused by the insertion/removal, produce unwanted 65 changes and/or erroneous operations. The insertion/removal of an electrical component will, by reason of contact bounce and similar phenomena, produce unde
sired changes in electrical voltages on the conductors connected thereto. These undesired voltage changes can be catastrophic. For example, the undesired voltage changes may alter a word on a data or address bus which can result in: execution of an incorrect instruction; or access of an incorrect memory address (for either a read or a write operation).
The consequences of noise on a data or address bus has been recognized in the prior art, see Hartlipp et al U.S. Pat. No. 3,548,177; Shutler U.S. Pat. No. 3,548,176 and Carnevale U.S. Pat. No. 3,548,178. In these patents, a noise detector is provided in the computer system which, in the presence of noise, initiates some action to inhibit or minimize the consequences of the noise. These references are not related to memory cartridges which can be inserted/removed, require the addition of noise detector hardware, and may slow down machine execution
SUMMARY OF THE INVENTION
In contrast the present invention recognizes that if the noise can be isolated, the harmful effects can be limited or eliminated. The present invention relates to a computer system which includes provision for memory cartridges which can be inserted/removed and includes at least two separate buses, wherein each bus may include address conductors, data conductors, and control conductors. The first of these two buses is dedicated to the fixed or immovable components which for example includes a central processing unit, read/write memory and read only storage, and may also include additional peripheral equipment such as input apparatus or output apparatus. The second or cartridge bus is the bus to which a memory cartridge is connected when the memory cartridge is inserted, and from which the memory cartridge is disconnected when a memory cartridge is removed. Obviously the system bus and the cartridge bus cannot be entirely divorced, since if that were the case the CPU could never obtain access to any memory cartridge. Rather, isolating logic is coupled between the system bus and the cartridge bus, the isolating logic provides isolation except when access is required to address space which resides on the cartridge bus. To the extent that the isolating logic decouples the cartridge bus from the system bus; the noise on a cartridge bus will not be reflected on the system bus. It is then only necessary to require that when a memory cartridge is being inserted/removed, that the isolating logic is controlled so as to maintain isolation between the cartridge bus and the system bus. In accordance with the invention the isolation is maintained by the presence of an idle loop which does not require access to the cartridge bus.
In a particular embodiment of the invention the computer system which includes provision for plug in memory cartridges may be a typewriter or word processor. In systems of this sort, the system is executing tasks (operating) only in response to operator requests For example the operator may be inserting text into read/write memory, this requires operator actuation of an input device such as a keyboard; alternatively the operator may request the printing of text from read/write memory, and this too requires operator action to initiate the printing. The invention is implemented in such a typewriter or word processor by providing the program with an idle loop which is operative in the absence of execution of a task requested by an operator. The idle
loop does not require access to the cartridge bus and tridge bus for isolating the system bus and the cartridge
thus the isolation is effective during execution to de- bus except when access is required to the cartridge bus.
couple system and cartridge buses. During this period Finally, the apparatus includes an arrangement for lim
of time the operator can insert/remove memory car- iting the central processor from execution on the system
tridges without affecting the system components cou- 5 bus unless the operator requests a task to be performed,
pled to the system bus since the decoupled state pre- nFsrRTPTiON Of Thf nHAWivns
vents any noise present on the cartridge bus from reach- BRIEF DESCRIPTION OF THE DRAWINGS
ing the system bus. This operation is assured by instruct- The present invention will be further described in the
ing the operator that cartridge removal/inserted is only following portions of this specification when taken in
effected when operator initiated commands are not 10 conjunction with the attached drawings in which like
being executed. Since the operator's attention would reference characters identify identical apparatus and in
normally be directed to memory cartridge insertion/- which:
removal, under normal circumstances operator invoked FIG. 1 is a block diagram of a computer system
commands would not be executed simultaneously with which includes provision for insertion/removal of
cartridge insertion/removal. 15 memory cartridges;
The invention can be employed by providing the FIG. 2 is an embodiment of software routines imple
system ROS with a program which includes the idle menting the invention.
loop, and which provides for the appropriate control of nFSrn Iption Of Thf the isolating logic to decouple the cartridge and the ^fJSSSn Fmsstmsn? system bus except during those times when apparatus 20 PREfrfcRREU EMBOD1MEN 1 coupled to the cartridge bus is invoked. An alternative FIG. 1 shows an example of a computer system scheme, which does not require the system ROS to which includes memory cartridges which may be ininclude the idle routine can be effected by recognizing serted and removed. More particularly, the computer that in many systems the program stored in the system system 10 includes a fixed series of components includROS is not executed from the ROS itself. Rather, in 25 ing CPU 100, ROS 105, RAM 110, an input device 130 those systems initial program steps transfer the program and an output device 140. All these devices are interfrom the system ROS to system RAM, and the program connected by system bus 150 through connectors 111, is executed out of RAM. Accordingly, in order to pre- 106, 107, 137 and 147. In addition, the system 10 provent disturbances occasioned by memory cartridge vides a slot 116 for a memory cartridge 115. When removal, the idle routine may be contained in the mem- 30 inserted in the slot 116 the memory cartridge 115 is ory cartridge itself. Here, cartridge insertion necessarily connected to the bus 165 via the connector 117. As requires that the system be powered down. When the shown in FIG. 1, a second slot 126 may be provided system is powered up, the idle routine from the memory which, when filled with a memory cartridge is concartridge itself is transferred to system RAM. The idle nected to the bus 165 via the connector 127. routine thus is executed out of system RAM and pro- 35 The slot 126 may be used for memory in the form of vides for the appropriate isolation so that on memory additional ROS or RAM. Obviously, the number of cartridge removal, the isolation ensures the decoupling slots can be increased beyond the two which are illusof the cartridge bus and system bus. trated. The system bus 150 is coupled to cartridge bus Thus in accordance with one aspect, the invention 165 via isolation logic 160. The isolation logic 160 is provides, in a computer system arranged to perform 40 available in typical commercially available devices and tasks initiated at operator request, which system in- is described in the Intel iAPX 86, 88 User's Manual eludes a central processor and main memory unit con- (August 1981) as including latch, buffer and transceivnected by a system bus, and in which at least some of ers. Isolation logic 160 is responsive to signals carried said tasks require additional memory cartridges, a over address and/or control conductors of the system method of inhibiting errors caused by the insertion/- 45 bus 150 to allow coupling of bus 150 to bus 165 only removal of a memory cartridge, said method compris- when address space connected to bus 165 is accessed, ing the steps of: There may be further cartridge buses coupled to the
(a) providing a cartridge bus to which memory car- system bus 150 via other isolation logic modules. The tridges are connected/disconnected on insertion/remo- system 10 is subject to the prior art deficiencies in that val, 50 when a memory cartridge such as ROS 115 is inserted/
(b) providing a controllable isolation between said removed the act of insertion/removal produces noise on system bus and said cartridge bus, and the bus 165 which can adversely affect the performance
(c) providing an idle loop for said central processor of any of the devices connected thereto. Specifically, effective except at times when an operator requests a since the isolation logic 160 may allow signals to pass task to be performed, which idle loop does not provide 55 from one bus to the other, there is no guarantee that for access to said cartridge bus. noise on bus 165 will be isolated from system bus 150.
In another aspect, the invention provides in a com- In one prior art system fixed ROS 105 provided es
puter system arranged to perform tasks initiated at oper- sentially no operating functions except support for func
ator request, which system includes a central processor tions directed by a feature cartridge such as ROS 115.
and a main memory interconnected by a system bus and 60 The typical ROS 115 maintained the CPU 100 execut
in which at least some of said tasks require additional ing in a tight loop of instructions from ROS 115. In such
memory cartridges, apparatus for inhibiting errors a system the insertion/removal of any other cartridge
caused by the insertion/removal of a memory cartridge. (such as in slot 126) was almost surely to generate erro
The apparatus includes a cartridge bus associated with neous execution since the logic 160 was almost continu
apparatus for connecting/disconnecting memory car- 65 ously maintained in a condition to couple bus 150 to bus
tridges to the cartridge bus on insertion/removal. The 165 (for instruction fetch). We have recognized that to
apparatus further includes a controllable isolation logic the extent that the isolating logic 160 decouples the
which is coupled between the system bus and the car- cartridge bus 165 from the system bus 150, then noise