A core logic chip set in a computer system provides a bridge between processor host and memory buses and a plurality ol peripheral component interconnect ("PCI") buses capable ol operating at 66 MHz. Each ol the plurality ol PCI buses have the same logical bus number. The core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device connected to the plurality ol PCI physical buses. Each ol the plurality ol PCI buses has its own read and write queues to provide transaction concurrency ol PCI devices on different ones ol the plurality ol PCI buses when the transaction addresses are not the same or are M byte aligned. Upper and lower memory address range registers store upper and lower memory addresses associated with each PCI device. Whenever a transaction occurs, the transaction address is compared with the stored range ol memory addresses. II a match between addresses is found then strong ordering is used. II no match is found then weak ordering may be used to improve transaction latency times. PCI device to PCI device transactions may occur without being starved by CPU host bus to PCI bus transactions.
55 Claims, 15 Drawing Sheets
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