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US006839006B1
(12) United States Patent ao) Patent No.: us 6,839,006 Bi
Sakai et al. (45) Date of Patent: Jan. 4,2005
(54) COMMUNICATION DEVICE
(75) Inventors: Takahisa Sakai, Amagasaki (JP); Yuji Mizuguchi, Hirakata (JP); Toshitomo Umei, Settsu (JP); Noboru Katta, Itami (JP)
(73) Assignee: Matsushita Electric Industrial Co., Ltd., Osaka (JP)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 10/771,062
(22) Filed: Feb. 4, 2004
(30) Foreign Application Priority Data
Dec. 10, 2003 (JP) 2003-412369
(51) Int. C I. H03M 7 12
(52) U.S. CI 341/70; 341/100
(58) Field of Search 341/50, 51, 53,
341/70, 100, 105; 375/130, 136, 150, 152, 282, 333, 361
(56) References Cited
U.S. PATENT DOCUMENTS
4,992,790 A * 2/1991 Montgomery 341/70
5,862,005 A * 1/1999 Leis et al 360/27
6,278,864 Bl * 8/2001 Cummins et al 455/73
6,363,107 Bl * 3/2002 Scott 375/150
6,768,433 Bl * 7/2004 Toth et al 341/105
FOREIGN PATENT DOCUMENTS
WO 02/30075 4/2002
* cited by examiner
Primary Examiner—Michael Tokar
Assistant Examiner—Linh V Nguyen
(74) Attorney, Agent, or Firm—-Wenderoth, Lind & Ponack,
L.L.P.
(57) ABSTRACT
An S/P converter 120 converts input data from serial to parallel for every two bits in different timings, thereby outputting two types of parallel data. Based on the input data, a timing detector 130 detects a timing which corresponds to boundaries between bits of a data portion before biphase encoding. Based on the detection result of the timing detector, a selector 140 selects either one of the two types of parallel data output from the S/P converter 120.
15 Claims, 16 Drawing Sheets
