Multiprocess execution system that designates cache use priority based on ...

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United States Patent [19]

Ozawa

US005787490A [ii] Patent Number: [45] Date of Patent:

5,787,490 Jul. 28, 1998

[54] MULTIPROCESS EXECUTION SYSTEM

THAT DESIGNATES CACHE USE PRIORITY
BASED ON PROCESS PRIORITY

[75] Inventor: Toshihiro Ozawa, Kawasaki, Japan

[73] Assignee: Fujitsu Limited. Kanagawa, Japan

[21] Appl. No.: 661,083

[22] Filed: Jun. 10,1996

[30] Foreign Application Priority Data

Oct. 6, 1995 [JP] Japan 7-259824

[51] Int CI.6 G06F 12/08

[52] U.S. CI 711/173; 711/158; 395/673

[58] Field of Search 395/673, 674,

395/497.04, 485, 403. 457; 711/173, 158,

3. 130

[56] References Cited

U.S. PATENT DOCUMENTS

4,654,782 3/1987 Bannai et al 395/403

5,109,512 4/1992 Bahretal _ 395/673

5,185,861 2/1993 Valencia 395/200.03

5,193,172 3/1993 Arai et al 395/674

5,287,508 2/1994 Hejna, Jr. et al 395/672

5,317,738 5/1994 Cochocroft, Jr. et al 395/673

5,446,893 8/1995 Uehara 395/675

5,465,342 11/1995 Walsh 395/446

OTHER PUBLICATIONS

Kirk et al., "Allocating SMART Cache for Schedulability", Euromicro Workshop on Real Time. pp. 41-50. Jan. 1991. Tanenbaum. Andrew S.. Modern Operating Systems, Prentice Hall. Upper Saddle River. NJ. pp. 119-128, 1992. Kirk, David B.. "SMART(Strategic Memory Allocation for Real-Time) Cache Desgin", Real-Time Systems. May 1989 Symposium, pp. 229-237.

Stone et al.. "Optimal Partitioning of Cache Memory". IEEE Transactions on Computers. V.41, No.9. pp. 1054-1068. Sep. 1992.

Primary Examiner—Tod R. Swann

Assistant Examiner—Christopher S. Chow

Attorney, Agent, or Firm—Armstrong. Westerman, Hattori,

McLeland & Naughton

[57] ABSTRACT

A cache use priority of a cache memory is designated by a cache use priority designation unit. In response to an access demand issued from a processing unit, a cache control unit controls the access to the cache memory in accordance with the cache use priority. In the case of a set associative cache for example, the number of ways and the number of blocks to be used within one set are varied based on the cache use priority of a process.

18 Claims, 13 Drawing Sheets