United States Patent [w]
Igarashi et al.
 CONTENTS ADDRESSABLE MEMORY
CIRCUIT FOR RETRIEVAL OPERATION IN
UNITS OF DATA BLOCKS
 Inventors: Kenji Igarashi; Toshiyuki Kanoh, both of Tokyo, Japan
 Assignee: NEC Corporation, Tokyo, Japan
 Appl. No.: 09/265,889
 Filed: Mar. 11, 1999
 Foreign Application Priority Data
Mar. 20, 1998 [JP] Japan 10-090643
 Int. C I. G11C 15/00
 U.S. CI 365/49; 365/189.07
 Field of Search 365/49, 189.07,
 References Cited
U.S. PATENT DOCUMENTS
4,958,377 9/1990 Takahashi 382/34
5,173,872 12/1992 Crawford et al 365/49
Patent Number: 6,081,442 Date of Patent: Jun. 27,2000
5,388,066 2/1995 Hamamoto et al 365/49
5,450,351 9/1995 Heddes 365/49
FOREIGN PATENT DOCUMENTS
0 814 416 12/1997 European Pat. Off. .
5-189979 7/1993 Japan .
Primary Examiner—Son Mai
Attorney, Agent, or Firm—Sughrue, Mion, Zinn, Macpeak & Seas, PLLC
A contents addressable memory circuit includes an inputting section, a contents addressable memory section and a control section. The inputting section divides an input data into n (n is an integer equal to or larger than 2) data blocks and supplies the n data blocks and an input address. The contents addressable memory section performs a data retrieving operation in units of data blocks to output addresses and coincidence flags corresponding to the data blocks. The coincidence flag is indicative of whether there is a data coincident with the corresponding data block. The control section outputs one of the outputted addresses based on the outputted addresses and the coincidence flags.
16 Claims, 5 Drawing Sheets