IIIH
US006907520B2
(12) United States Patent ao) Patent No.: us 6,907,520 B2
Parady (45) Date of Patent: Jun. 14,2005
(54) THRESHOLD-BASED LOAD ADDRESS PREDICTION AND NEW THREAD IDENTIFICATION IN A MULTITHREADED MICROPROCESSOR
(75) Inventor: Bodo K. Parady, Danville, CA (US)
(73) Assignee: Sun Microsystems, Inc., Santa Clara, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 569 days.
(21) Appl. No.: 10/044,487
(22) Filed: Jan. 11, 2002
(65) Prior Publication Data
US 2002/0091915 Al Jul. 11, 2002
Related U.S. Application Data
(60) Provisional application No. 60/261,435, filed on Jan. 11, 2001.
(51) Int. CI. G06F 9/00
(52) U.S. CI 712/228
(58) Field of Search 718/102; 712/207,
712/225, 228
(56) References Cited
U.S. PATENT DOCUMENTS
5,377,336 A * 12/1994 Eickemeyer et al 712/207
5,758,142 A * 5/1998 McFarling et al 712/239
5,822,788 A * 10/1998 Kahn et al 711/213
5,933,627 A * 8/1999 Parady 712/228
6,182,210 Bl * 1/2001 Akkary et al 712/235
OTHER PUBLICATIONS
Yoaz et al., "Speculation Techniques for Improving Load Related Instruction Scheduling," May 1999, pp. 42-53.* Chen et al., "Effective Hardware-Based Data Prefetching for High-Performance Processors," 1993, pp. 609-623.*
"Load Latency Tolerance In Dynamically Scheduled Processors"; IEEE 98; Srinivasan & Lebeck; Duke University, Department of Computer Science; Durham, North Carolina. "Discrete Last-Address Predictor"; Morancho, Llaberia, & Olive; Universitat Politecnica de Catalunya, Department d'Arquitectura de Computadores; Barcelona (Spain). "Understanding the Differences Between Value Prediction and Instruction Reuse"; Sodani & Sohi; University of Wisconsin-Madison, Computer Sciences Department; Madison, Wisconsin.
"The Predictability of Data Values"; Sazeides & Smith; University of Wisconsin-Madison, Department of Electrical and Computer Engineering; Madison, Wisconsin. "Speculative Execution via Address Prediction and Data Prefetching"; Gonzalez & Gonzalez; Universitat Politecnica de Catalunya, Department d'Arquitectura de Computadors; Barcelona (Spain).
* cited by examiner
Primary Examiner—Eddie Chan
Assistant Examiner—David J. Huisman
(74) Attorney, Agent, or Firm—Meyertons Hood Kivlin
Kowert & Goetzel, PC; Rory D. Rankin
A method and apparatus for predicting load addresses and identifying new threads of instructions for execution in a multithreaded processor. A load prediction unit scans an instruction window for load instructions. A load prediction table is searched for an entry corresponding to a detected load instruction. If an entry is found in the table, a load address prediction is made for the load instruction and conveyed to the data cache. If the load address misses in the cache, the data is prefetched. Subsequently, if it is determined that the load prediction was incorrect, a miss counter in the corresponding entry in the load prediction table is incremented. If on a subsequent detection of the load instruction, the miss counter has reached a threshold, the load instruction is predicted to miss. In response to the predicted miss, a new thread of instructions is identified for execution.
24 Claims, 7 Drawing Sheets
