Memory integrated circuit for storing digital and analog data and method

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US006044004A

United States Patent [w]

Kramer

[54] MEMORY INTEGRATED CIRCUIT FOR STORING DIGITAL AND ANALOG DATA AND METHOD

[75] Inventor: Alan Kramer, Berkeley, Calif.

[73] Assignee: STMicroelectronics, Inc., Carrollton, Tex.

[21] Appl. No.: 09/219,548 [22] Filed: Dec. 22, 1998

[51] Int. CI.7 G11C 27/00; G11C 16/06;

G11C 7/00

[52] U.S. CI 365/45; 365/185.03; 365/222

[58] Field of Search 365/45, 185.03,

365/222

[56] References Cited

U.S. PATENT DOCUMENTS

4,209,852 6/1980 Hyatt 365/222

4,280,196 7/1981 Hornak et al 365/45

5,592,418 1/1997 Sabatini et al 365/185.18

5,751,632 5/1998 Choi et al 365/185.03

5,815,425 9/1998 Wong et al 365/185.03

5,867,423 2/1999 Kapoor et al 365/185.03

OTHER PUBLICATIONS

Kramer et al., "Flash-Based Programmable Nonlinear Capacitor for Switched-Capacitor Implementations of Neural Networks," International Electron Devices Meeting 1994, San Francisco, CA, pp. 449-452, Dec. 11-14, 1994.

Patent Number: 6,044,004 Date of Patent: Mar. 28,2000

Kramer et al., "ISSCC97/Session 2/TD: Vision Processors & CAMs/Paper TP 2.4," 1997 IEEE International SolidState Circuits Conference, pp. 44-45, 1997.

Rolandi et al., "ISSCC98/Session 21/Memory: NV and Embedded/Paper SA21.2," 1998 IEEE International SolidState Circuits Conference, pp. 334-335, 1998.

Primary Examiner—Trong Phan

Attorney, Agent, or Firm—David V. Carlson; Theodore E. Galanthay; Lisa K. Jorgenson

[57] ABSTRACT

A memory device includes an array of floating gate FET memory cells capable of storing either analog or digital data. The memory device includes first read-write circuitry for storage and retrieval of digital data, and second read-write circuitry for storage and retrieval of analog data. As a result, the digital data storage capability facilitates real-time operation of devices using the memory device without sacrificing the memory capacity capabilities of analog data storage. When a host device using the memory device is not in use, the stored digital data may be read out from the memory device, converted to analog form and then stored in the memory device, re-capturing the data density capabilities of analog data storage in floating gate FET memory cells. Analog data latency comparable to digital data latency is achieved by reading the analog data out from the memory cells, refreshing the analog data and then re-storing digital or analog data corresponding to the refreshed analog data in the memory cells in response to predetermined criteria.

40 Claims, 5 Drawing Sheets