[54] FIELD PROGRAMMABLE GATE ARRAY WITH MULTI-PORT RAM
[75] Inventors: Kai-Kit Ngai, Allentown; Satwant Singh, Macungie, both of Pa.
[73] Assignee: Lucent Technologies Inc., Murray Hill, N.J.
[21] Appl. No.: 507,957
[22] Filed: Jul. 27,1995
[51] Int. CI.6 H03K 19/177
[52] U.S. CI 326/40; 326/39; 365/189.08
[58] Field of Search 326/37,39-41,
326/46, 47, 38; 365/189.08
[56] References Cited
U.S. PATENT DOCUMENTS
Re. 34,363 8/1993 Freeman 307/465
4,870,302 9/1989 Freeman 307/465
5,128,559 7/1992 Steele 365/189.08
5,255,221 10/1993 Hill 365/189.08
5,282,174 1/1994 Little 365/230.05
5,343,406 8/1994 Freeman 326/40
5,384,497 1/1995 Britton et al 326/44
5,386,156 1/1995 Britton et al 326/37
5,442,306 8/1995 Woo 326/40
FOREIGN PATENT DOCUMENTS
0177261B1 11/1990 European Pat. Off. H03K 19/177
OTHER PUBLICATIONS
Knapp, S. K. "XC4000E Edge-Triggered and Dual-Part RAM Capability". Xilinx, Inc., Jun. 20, 1995, pp. 1-3.
Cartier, L. "Implementing FIFOs in XC4000E RAM". Xilinx, Inc., Oct. 9, 1995. pp. 1-15.
"XC4000E Logic Cell Array Family", Product Preview, by
Xilinx, Inc., May 2, 1995, pp. 1-4.
Primary Examiner—Edward P. Westin
Assistant Examiner—Jon Santamauro
Attorney, Agent, or Firm—James H. Fox
[57] ABSTRACT
A field programmable gate array (FPGA) with a programmable function unit (PFU) that includes a look-up table (LUT) for implementing a plurality of functions including first and second RAM cells, and a programmable switching device dedicated to coupling and decoupling the RAM cells. The first and second RAM cells are coupled to respective first and second read/write ports. The RAM cells function individually as single-port RAM cells when decoupled by the switching device. However, the RAM cells share data to function collectively as a dual-port RAM cell when coupled by the switching device. The dual-port RAM cell is accessible by both the first and second read/write ports.
