[li] Patent Number: 4,819,207 [45] Date of Patent: Apr. 4,1989
[54] HIGH-SPEED REFRESHING RECHNIQUE FOR HIGHLY-INTEGRATED RANDOM-ACCESS MEMORY
[75] Inventors: Koji Sakui, Tokyo; Shigeyoshi
Watanabe, Yokohama, both of Japan
[73] Assignee: Kabushiki Kaisha Toshiba, Kawasaki, Japan
[21] Appl. No.: 99,601
[22] Filed: Sep. 22, 1987
[30] Foreign Application Priority Data
Sep. 30, 1986 [JP] Japan 61-231772
Mar. 2, 1987 [JP] Japan 62-46975
[51] Int. CI.* G11C7/00
[52] U.S. Q 365/222; 365/207
[58] Field of Search 365/222, 207, 208, 189
[56] References Cited
U.S. PATENT DOCUMENTS
4,367,540 1/1983 Shimohigashi 365/207
FOREIGN PATENT DOCUMENTS
60-253096 12/1985 Japan .
Primary Examiner—Joseph A. Popek
Attorney, Agent, or Firm—Obion, Fisher, Spivak,
McClelland & Maier
[57] ABSTRACT
A divided-bit line type dynamic random-access memory is disclosed which has parallel main bit line pairs in each of which sub-bit line pairs are provided to be electrically parallel with each other. Parallel word lines are provided on the substrate to insulatively cross the subbit line pairs. Memory cells are connected to crossing points of the sub-bit line pairs and the word lines. Main sense amplifiers are respectively connected to the main bit line pairs, sub-sense amplifiers are respectively connected to the sub-bit line pairs. A specific refreshing technique is utilized, according to which, when a refreshing operation is executed in a refreshing mode of the memory, the same number of word lines as that of sub-bit line pairs provided in each main-bit line pair are simultaneously selected, and the sub-sense amplifiers are activated to refresh together the memory cells which are connected to the work lines thus selected.
12 Claims, 3 Drawing Sheets
