[54] MEMBRANE DIELECTRIC ISOLATION IC FABRICATION
[76] Inventor: Glenn J. Leedy, 1061 E. Mountain Dr., Montecito, Calif. 93108
[21] Appl. No.: 474,449
[22] Filed: Jun. 7,1995
Related U.S. Application Data
[60] Continuation of Ser. No. 315,905, Sep. 30, 1994, which is a division of Ser. No. 865,412, Apr. 8, 1992, Pat. No. 5,354, 695.
[51] Int. CI.6 H01L 21/70
[52] U.S. CI 437/51; 437/40; 437/41;
437/966; 437/974
[58] Field of Search 437/51, 40 TFT,
437/41 TFT, 916, 966, 974; 148/DIG. 135
[56] References Cited
U.S. PATENT DOCUMENTS
4,070,230 1/1978 Stein 437/66
4,131,985 1/1979 Greenwood et al 437/62
4,618,397 10/1986 Shimizu et al 437/8
4,702,336 10/1987 Maedaetal 437/241
4,721,938 1/1988 Steveson 156/162
4,909,611 3/1990 Spooner 359/291
4,952,446 8/1990 Lee et al 437/974
5,071,510 12/1991 Findleretal 156/662
5,110,373 5/1992 Mauger 437/974
Primary Examiner—Trung Dang
Attorney, Agent, or Firm—Blakely, Sokoloff, Taylor & Zafman
[57] ABSTRACT
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
3 Claims, 64 Drawing Sheets
