Logic simulator using small capacity memories for storing logic states ...

United States Patent m

Nomizu et al.

[li] Patent Number: 4,782,440 [45] Date of Patent: Nov. 1, 1988

[54] LOGIC SIMULATOR USING SMALL

CAPACITY MEMORIES FOR STORING
LOGIC STATES, CONNECTION PATTERNS,
AND LOGIC FUNCTIONS

[75] Inventors: Nobuyoshi Nomizu; Tohru Sasaki, both of Tokyo, Japan

[73] Assignee: NEC Corporation, Tokyo, Japan

[21] Appl. No.: 761,281

[22] Filed: Aug. 1,1985

[30] Foreign Application Priority Data

Aug. 3, 1984 [JP] Japan 59-162843

[51] Int. a.* G06F 15/20; G06F 7/38

[52] U.S. Q 364/200; 364/900;

364/578; 371/23

[58] Field of Search ... 364/200 MS File, 900 MS File,

364/716, 578; 371/25, 23

[56] References Cited

U.S. PATENT DOCUMENTS

3,934,231 1/1976 Armstrong 364/900

3,961,250 1/1976 Snethen 371/25

4,120,043 10/1978 Su 364/716

4,306,286 12/1981 Cocke et al 364/200

4,324,093 7/1982 Miyoshi 364/578

4,527,249 7/1985 Van Brunt 364/578

4,541,071 9/1985 Ohmori 364/900

4,587,625 5/1986 Marino, Jr. et al 364/578

4,628,471 12/1986 Schuler et al 371/23

4,656,580 4/1987 Hitchcock, Sr. et al 364/200

4,697,241 9/1987 Lavi 364/900

4,725,975 2/1988 Sasaki 364/900

Primary Examiner—Raulfe B. Zache
Assistant Examiner—Danh Phung
Attorney, Agent, or Firm—Sughrue, Mion, Zinn,
Macpeak & Seas

[57] ABSTRACT

A logic simulator for simulating operation of a logic circuit is provided with gates divisible into successive levels according to a connection pattern between the gates. A pattern memory (16) memorizes the connection pattern as a bit sequence representative of direct connections between each gate of each level to the gates of a preceding level. A function memory (17) memorizes logic functions of the respective gates. Responsive to input logic states of each level, the bit sequence for the gates of the level under consideration, and the logic functions of the respective gates of that level, a calculator (25) calculates output logic states of that level as input logic states of a succeeding level successively for the gates of the level in question. For a higher speed of simulation, the logic circuitry may be divided into a predetermined number of gate groups, each consisting of gates of the successive levels. Each of the pattern and the function memories is divided into parts for the respective gate groups. In order to make the logic simulator have a further reduced memory capacity, the gates of each preceding level may be classified into gate blocks. A block specifier is additionally used. Under the circumstances, it is sufficient that each bit sequence should represent direct connections to the gate blocks. The calculator is supplied with the output logic states of each gate block.

4 Claims, 3 Drawing Sheets