Passivation method and structure for a ferroelectric integrated circuit ...

United States Patent [19]

Argos, Jr. et al.

[54] PASSIVATION METHOD AND STRUCTURE FOR A FERROELECTRIC INTEGRATED CIRCUIT USING HARD CERAMIC MATERIALS OR THE LIKE

[75] Inventors: George Argos, Jr.; John D. Spano;

Steyen D. Traynor, all of Colorado
Springs, Colo.

[73] Assignee: Ramtron International Corporation,

Colorado Springs, Colo.

[21] Appl. No.: 212,495

[22] Filed: Mar. 11,1994

[51] Int. Cl.« H01L 21/02

[52] U.S. CI 437/235; 437/238;

437/240; 437/919; 437/978

[58] Field of Search 148/DIG. 148; 437/238;

365/145; 257/295; 437/235, 240, 919, 980

[56] References Cited

U.S. PATENT DOCUMENTS

4,040,874 8/1977 Yerman 437/235

4,149,302 4/1979 Cook 29/25.42

4,675,715 6/1987 Lepselter et al 257/915

4,757,028 7/1988 Kondoh et al 437/40

4,759,823 7/1988 Asselamis et al 156/659.1

4,811,078 3/1989 Tigelaar et al 257/915

4,860,254 8/1989 Pott et al 365/145

5,024,964 6/1991 Rohrer et al 437/47

5,040,046 8/1991 Chhabra et al 437/238

5,043,049 8/1991 Takenaka 204/192.15

5,081,559 1/1992 Fazan et al 361/313

5,119,154 6/1992 Gnadinger 257/298

5,122,923 6/1992 Matsubara et al 361/321

5,124,014 6/1992 Foo et al 437/238

5,266,355 11/1993 Wemberg et al 427/248.1

FOREIGN PATENT DOCUMENTS

415751A1 3/1991 European Pat. Off. .

59- 105364 6/1984 Japan 257/915

60- 100464 6/1985 Japan 257/915

[li] Patent Number: 5,438,023 [45] Date of Patent: Aug. 1,1995

63-023069 7/1988 Japan H01L 29/78

1-253257 10/1989 Japan 257/915

1-265524 10/1989 Japan 257/915

1- 241860 12/1989 Japan H01L 27/04

2- 183566 7/1990 Japan 257/915

2-184079 7/1990 Japan 257/915

Primary Examiner—Olik Chaudhuri
Assistant Examiner—H. Jey Tsai
Attorney, Agent, or Firm—Peter J. Meza

[57] ABSTRACT

A method for passivating an integrated circuit includes the RF sputtering of a hard passivation layer on the surface of the integrated circuit. The hard passivation layer can be a ceramic material such as various doped and undoped titanates, zirconates, niobates, tantalates, stanates, hafnates, and manganates, in either their ferroelectric or non-ferroelectric phases. Other exotic, hard, and usually non-ferroelectric materials not normally found in integrated circuit processing such as carbides may also be used. If the integrated circuit sought to be passivated contains ferroelectric devices, the hard passivation layer can be fabricated out of the same material used in the integrated ferroelectric devices. An optional silicon dioxide insulating layer can be deposited on the surface of the integrated circuit before the hard passivation layer is deposited. The optional silicon dioxide layer is used to prevent any possible contamination of the integrated circuit by the passivation layer. Similarly, an optional sealing layer such as silicon dioxide, silicon nitride, or polymer based materials can be deposited on top of the passivation layer to prevent any possible contamination of the integrated circuit package by the passivation layer. Once the hard passivation layer and any optional layers are formed, these layers are etched to provide access to underlying integrated circuit bonding pads.

11 Claims, 4 Drawing Sheets