(54) SYSTEM AND METHOD FOR AN
ACCURACY-ENHANCED DLL DURING A
MEASURE INITIALIZATION MODE
(75) Inventor: Jongtae Kwak, Boise, ID (US)
(73) Assignee: Micron Technology, Inc., Boise, ID (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 399 days.
(21) Appl.No.: 11/588,954
(22) Filed: Oct. 27, 2006
(65) Prior Publication Data
US 2008/0189568 Al Aug. 7, 2008
(51) Int. CI.
H03L 7/06 (2006.01)
(52) U.S. CI 327/158; 327/156; 327/159
(58) Field of Classification Search 327/156,
327/158,159; 331/25,34; 375/373,375,
See application file for complete search history.
(56) References Cited
U.S. PATENT DOCUMENTS
6,060,928 A 5/2000 Jun et al 327/261
6,100,735 A 8/2000 Lu 327/158
6,313,675 Bl 11/2001 Naffziger 327/158
6,546,530 Bl 4/2003 Drepsetal 716/6
A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.
33 Claims, 6 Drawing Sheets