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US006289441B1
(12) United States Patent ao) Patent No.: us 6,289,441 Bi
Talcott et al. (45) Date of Patent: Sep. 11,2001
(54) METHOD AND APPARATUS FOR
PERFORMING MULTIPLE BRANCH
PREDICTIONS PER CYCLE
(75) Inventors: Adam R. Talcott, San Jose; Ramesh K. Panwar, Santa Clara; Rajasekhar Cherabuddi, Cupertino; Sanjay Patel,
Fremont, all of CA (US)
(73) Assignee: Sun Microsystems, Inc., Palo Alto, CA (US)
( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 09/005,076
(22) Filed: Jan. 9, 1998
(51) Int. CI.7 G06F 9/38
(52) U.S. CI 712/239; 712/240
(58) Field of Search 712/237, 238,
712/239, 240
(56) References Cited
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5,687,338 * 11/1997 Boggs et al 712/205
5,758,112 * 5/1998 Yeager et al 712/217
5,796,998 * 8/1998 Levitan et al 712/239
5^854,761 * 12/1998 Patel et al 365/49
5,857,098 * 1/1999 Talcott et al 712/240
5,870,599 * 2/1999 Hinton et al 712/239
5,875,325 * 2/1999 Talcott 712/240
OTHER PUBLICATIONS
Yeh et al., "A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution," Proceedings of the 25th Annual International Symposium on Microarchitecture, Micro 25, IEEE, pp. 129-139, Dec. 1-4, 1992.*
* cited by examiner
Primary Examiner—-William M. Treat
(74) Attorney, Agent, or Firm—Townsend and Townsend
and Crew LLP
(57) ABSTRACT
A method and apparatus for performing multiple branch predictions per cycle is disclosed. The method and apparatus according to the present invention determine, within one fetch cycle, which instructions in a plurality of fetch instructions are branches and whether such branches are taken or not taken thereby finding the oldest taken branch, which has a target address that is fetched within the same fetch cycle.
19 Claims, 7 Drawing Sheets
