Memory device

(54) MEMORY DEVICE

(75) Inventor: Kenji Funamoto, Asaka (JP)

(73) Assignee: Fuji Photo Film Co., LTD,

Minami-Ashigara (JP)

( * ) Notice: Subject to any disclaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 216 days.

(21) Appl. No.: 10/765,956

(22) Filed: Jan. 29, 2004

(65) Prior Publication Data

US 2004/0184306 Al Sep. 23, 2004

(30) Foreign Application Priority Data

Jan. 30, 2003 (JP) 2003-021381

(51) Int. CI.

G06F13/40 (2006.01)

G06F 3/00 (2006.01)

G06F13/12 (2006.01)

G06F15/16 (2006.01)

G09G 5/399 (2006.01)

G06F 13/20 (2006.01)

(52) U.S. CI 710/307; 710/53; 710/66;

345/539

(58) Field of Classification Search 345/539

See application file for complete search history.

(56) References Cited

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FOREIGN PATENT DOCUMENTS

JP 11-250228 9/1999

* cited by examiner

Primary Examiner—Paul R. Myers
Assistant Examiner—Ryan Stiglic

(74) Attorney, Agent, or Firm—McGinn IP Law Group, PLLC

A memory device is so adapted that data processing time is not prolonged even when there is little bus width. A DRAM is connected to first to third buffer circuits by buses, which have a bus width of 128 bits, via a selector. The first to third buffer circuits are connected to a circuit such as a signal processing circuit by buses having a bit width of 32 bits. Since part of the circuitry is connected by buses having a bit width of 32 bits, the wiring is simple. By executing various processing in parallel, it is possible to prevent prolongation of the time required to record image data on a memory card.

18 Claims, 3 Drawing Sheets