[54] PSEUDO-LRU CACHE MEMORY
REPLACEMENT METHOD AND APPARATUS
UTILIZING NODES
[75] Inventors: Michael B. Smith, Mississauga;
Michael J. Tresidder, Scarborough,
both of Canada
[73] Assignee: LSI Logic Corporation, Milpitas,
Calif.
[21] Appl. No.: 443,887
[22] Filed: May 31,1995
Related U.S. Application Data
[63] Continuation-in-part of Ser. No. 376,152, Jan. 20, 1995, abandoned, which is a continuation-in-part of Ser. No. 362,409, Dec. 23,1994, and Ser. No. 363,237, Oct. 23,1994.
[51] Int. CI.6 G06F 12/00; G06F 12/02;
G06F 13/00
[52] U.S. CI 395/463; 395/445; 395/460;
395/481; 395/486; 395/48; 364/DIG. 1
[58] Field of Search 395/445, 444,
395/460, 461, 463, 466, 487; 364/DIG. 1
[56] References Cited
U.S. PATENT DOCUMENTS
5,185,861 2/1993 Valencia 395/471
5,218,687 6/1993 Ducousso et al 395/455
5,261,053 11/1993 Valencia 395/460
5,295,253 3/1994 Ducousso et al 395/417
5,325,504 6/1994 Tipley et al 395/455
5,325,511 6/1994 Collins et al 395/455
5,329,627 7/1994 Nanda et al 395/417
5,353,425 10/1994 Malamey et al 295/471
Primary Examiner—Tod R. Swann
Assistant Examiner—Tuan V. Thai
Attorney, Agent, or Firm—Riches, McKenzie & Herbert
[57] ABSTRACT
An apparatus and method implementing an algorithm for determining the most likely least recently used cache line in a cache so that this cache line can be written back to main memory. This algorithm is implemented on a bus control unit bridging a 50 Mhz multi-processor interconnect bus with a 33 Mhz peripheral component interconnect bus through an asynchronous interface. All data being transferred between the multi-processor interconnect bus and the peripheral component interconnect bus must pass through the input/output cache on the bus control unit. The algorithm determines a unique locating path to the last used cache lines and from this determines a unique locating path to a memory location which likely contains a least recently used cache line which can then be written back to main memory. Each memory location is identified by a unique locating path which passes through a nodal tree. Each node on the lowest level of nodes is associated with two memory locations, and, each pair of nodes is associated with one node on a next high level of nodes. Each node is associated with a bit in a register which is used to identify and record the unique path through the nodes of the cache lines being used and stored. The unique locating path to the memory location with the cache lines to be written back to memory, or otherwise evicted, is determined based on the stored value of bits.
19 Claims, 4 Drawing Sheets
