United States Patent  [ii] Patent Number: 4,819,251
Nelson  Date of Patent: Apr. 4,1989
 HIGH SPEED NON-RETURN-TO-ZERO
DIGITAL CLOCK RECOVERY APPARATUS
 Inventor: Blaine J. Nelson, Piano, Tex.
 Assignee: Rockwell International Corporation, El Segundo, Calif.
 Appl. No.: 190,913
 Filed: May 6,1988
 IntCl.4 H03L7/00
 U.S. Q 375/119; 331/1 A;
 Field of Search 375/81, 119, 120;
331/1 A, 19; 328/38, 63, 74, 75, 155
 References Cited
U.S. PATENT DOCUMENTS
3,935,538 1/1976 Kizler et al 328/74
4,641,323 2/1987 Tsang 375/119
4,733,197 3/1988 Chow 331/1 A
Primary Examiner—Benedict V. Safourek
Attorney, Agent, or Firm—Bruce C. Lutz; V. Lawrence
Sewell; H. Fredrick Hamann
A digital clock recovery circuit is presented which uses a delay line to produce a plurality of delayed sample signals. The sample signals are used to sample incoming data in a phase detector and the resultant sampled data is then resampled by the tentatively correct apparatus clock output signal. The resampled data provides a direct indication of the phase difference beween the data and the clock and the value can be obtained using a summing circuit. If the summed amount is outside an allowable range of values, a phase altering signal is supplied to an oscillator to change the phase of the apparatus clock output signal.
5 Claims, 6 Drawing Sheets