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US006852571B2
(12) United States Patent ao) Patent No.: us 6,852,571 B2
Matsuura et al. (45) Date of Patent: Feb. 8,2005
(54) METHOD OF MANUFACTURING STACKED SEMICONDUCTOR DEVICE
(75) Inventors: Tetsuya Matsuura, Hyogo (JP);
Tomoaki Hashimoto, Hyogo (JP)
(73) Assignee: Renesas Technology Corp., Tokyo (JP)
( * ) Notice: Subject to any disclaimer, the term ol this patent is extended or adjusted under 35 U.S.C. 154(b) by 0 days.
(21) Appl. No.: 10/654,900
(22) Filed: Sep. 5, 2003
(65) Prior Publication Data
US 2004/0180471 Al Sep. 16, 2004 (30) Foreign Application Priority Data
Mar. 14, 2003 (JP) 2003-069724
(51) Int. CI.7 H01L 21/44; H01L 21/48;
H01L 21/50
(52) U.S. CI 438/107; 438/109; 438/112;
438/124; 438/612; 438/617
(58) Field of Search 438/107, 127,
438/109, 112, 124, 126, 618, 617, 666,
110
(56) References Cited
U.S. PATENT DOCUMENTS
6,316,838 Bl * 11/2001 Ozawa et al 257/778
6,388,313 Bl * 5/2002 Lee et al 257/686
6,407,456 Bl * 6/2002 Ball 257/777
6,503,776 B2 * 1/2003 Pai et al 438/106
6,593,662 Bl * 7/2003 Pu et al 257/777
6,650,019 B2 * 11/2003 Glenn et al 257/777
6,670,701 B2 * 12/2003 Matsuura et al 257/686
6,759,307 Bl * 7/2004 Yang 438/455
2002/0090753 Al * 7/2002 Pai et al 438/108
2003/0176018 Al * 9/2003 Derderian 438/109
2004/0009631 Al * 1/2004 Connell et al 438/127
2004/0097017 Al * 5/2004 Shimanuki 438/124
2004/0126910 Al * 7/2004 Thomas et al 438/15
2004/0145039 Al * 7/2004 Shim et al 257/678
2004/0157375 Al * 8/2004 Derderian 438/118
FOREIGN PATENT DOCUMENTS
JP 5-29402 2/1993
JP 5-258986 10/1993
JP 2000-216333 A 8/2000
JP P2002-231885 A 8/2002
* cited by examiner
Primary Examiner—Matthew Smith
Assistant Examiner—Chuong Anh Luu
(74) Attorney, Agent, or Firm—McDermott, Will & Emery
LLP
(57) ABSTRACT
Flux is supplied to the surface ol each land by a flux supplying apparatus. A solder ball having a predetermined size is supplied onto a land by using a ball supplying apparatus. A memory IC is disposed on a logic IC and each ol a plurality ol external leads comes into contact with a predetermined position in each ol a plurality ol corresponding lands. By performing predetermined heat treatment, the solder ball is melted to bond each external lead and each land with each other. After that, the melted solder is cooled down, the bonded portion is formed, and a stacked semiconductor device in which the memory IC is stacked on the logic IC is completed. In such a manner, a stacked semiconductor device in which external leads of a semiconductor device body are bonded to electrodes on a substrate securely is obtained.
9 Claims, 21 Drawing Sheets
