Gerald George Pechanek, Cary, NC (US); Charles W. Kurak, Jr., Durham, NC (US); Larry D. Larsen, Raleigh, NC (US)
Altera Corporation, San Jose, CA (US)
10/848,615 May 18, 2004
(Under 37 CFR1.47)
An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray architecture for application to high-volume and portablke battery-powered type of products.
In the ManArray abbreviation process a standard 32-bit ManArray instruction is reduced to a smaller length instruction format, such as 14-bits. An application is first programmed using the full ManArray instruction set using the native 32-bit instructions. After the application program is completed and verified, an instruction-abbreviation tool analyzes the 32-bit application program and generates the abbreviated program using the abbreviated instructions. This instruction abbreviation process allows different programreduction optimizations tailored for each application program. This process develops an optimized instruction set for the intended application. The abbreviated program, now located in a significantly smaller instruction memory, is functionally equivalent to the original native 32-bit application program. The abbreviated-instructions are fetched from this smaller memory and then dynamically translated into native ManArray instruction form in a sequence processor controller. Since the instruction set is now determined for the specific application, an optimized processor design can be easily produced. The system and process can be applied to native instructions having other numbers of bits and to other processing architectures.
57 Claims, 20 Drawing Sheets